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Faculty for IP Firmware At STMicroelectronics
Posted July 25, 2011
· 1 - 3 Years
Organization
STMicroelectronics is one of the world's largest semiconductor companies with net revenues of US$ 10.35 billion in 2010. Offering one of the industry's broadest product portfolios, ST serves customers across the spectrum of electronics applications with innovative semiconductor solutions by leveraging its vast array of technologies, design expertise and combination of intellectual property portfolio, strategic partnerships and manufacturing strength.
Role
Designation IP Firmware /Design Engineer
Job Description
Job Summary:
The Firmware Engineer will be part of Interface IP design Team of HED CHD R&D .
The Interface IP design team, design and develop H/W based IPs as well as firmware based complex IP(s). This team delivers
the next generation Interface IP used in CHD Set Top Box System on Chip and Other ST's division.
Key Responsibilities:
Candidate will responsible for delivering high quality Core-Based IP for CHD SOC , CHD Driver and validation Team. He/She
will work with System/Product/IP Architecture team to come up next generation IP Functionality.
To gather the requirement for IP's functionality form system Architecture, Product Architecture and IP Architecture team as
well as from Software Driver and Validation team.
To design and develop firmware code as much reusable as possible that matches with the project requirements using the FW
platforms and document it.
To design the FDMA and other IP(s) SystemC Model to use in early software development flow.
To Verify the Firmware using multiple abstractions like Simulation Platform, SOC Verification and Silicon level.
Document all the design activities by Design Specification, Feasibility report, Technical report, Evaluation report, etc.
To support the SOC verification, validation, software driver and FAEs at all aspect in supply chain flow.
Desired Profile
The job requirement for the IP designer includes but not limited to following domains and skill set:
Very proficient in CPU architecture and micro-controller and digital design concepts.
Proficient in C/C++/Data Structure/SystemC and Unix/Linux Environment and development platform.
Good knowledge of scripting language like PERL, SHELL etc.
The Other skills required are Basic knowledge of IC design flow.
Knowledge of ON-CHIP BUS Architecture (AHB/AXI etc) and embedded software, RTOS will be desirable.
Tool Chain like ncsim, gnu compiler, debugger, profiler etc will be plus.
Good documentation and communication skills
Very Good problem solving and debugging skill.
Experience 1 - 3 Years
Industry Type Semiconductors/ Electronics
Role Database Architect/Designer
Functional Area Embedded/EDA /VLSI/ASIC/Chip Design
Education UG - B.Tech/B.E. - Electronics/Telecomunication
PG - M.Tech - Electronics/Telecomunication
Compensation: As per Industry Standards
Location Delhi/NCR
Keywords like Simulation Platform, SOC Verification,Silicon level,CHD SOC , CHD Driver
Contact ST- HR
STMicroelectronics Pvt Ltd
Plot No. - 01, Knowledge Park -3,
Greater Noida
NOIDA,Uttar Pradesh,India 201308
Telephone 91-120-2352999
Website http://www.st.com/internet/com/home/home.jsp
Job Description
Job Summary:
The Firmware Engineer will be part of Interface IP design Team of HED CHD R&D .
The Interface IP design team, design and develop H/W based IPs as well as firmware based complex IP(s). This team delivers
the next generation Interface IP used in CHD Set Top Box System on Chip and Other ST's division.
Key Responsibilities:
Candidate will responsible for delivering high quality Core-Based IP for CHD SOC , CHD Driver and validation Team. He/She
will work with System/Product/IP Architecture team to come up next generation IP Functionality.
To gather the requirement for IP's functionality form system Architecture, Product Architecture and IP Architecture team as
well as from Software Driver and Validation team.
To design and develop firmware code as much reusable as possible that matches with the project requirements using the FW
platforms and document it.
To design the FDMA and other IP(s) SystemC Model to use in early software development flow.
To Verify the Firmware using multiple abstractions like Simulation Platform, SOC Verification and Silicon level.
Document all the design activities by Design Specification, Feasibility report, Technical report, Evaluation report, etc.
To support the SOC verification, validation, software driver and FAEs at all aspect in supply chain flow.
Desired Profile
The job requirement for the IP designer includes but not limited to following domains and skill set:
Very proficient in CPU architecture and micro-controller and digital design concepts.
Proficient in C/C++/Data Structure/SystemC and Unix/Linux Environment and development platform.
Good knowledge of scripting language like PERL, SHELL etc.
The Other skills required are Basic knowledge of IC design flow.
Knowledge of ON-CHIP BUS Architecture (AHB/AXI etc) and embedded software, RTOS will be desirable.
Tool Chain like ncsim, gnu compiler, debugger, profiler etc will be plus.
Good documentation and communication skills
Very Good problem solving and debugging skill.
Experience 1 - 3 Years
Industry Type Semiconductors/ Electronics
Role Database Architect/Designer
Functional Area Embedded/EDA /VLSI/ASIC/Chip Design
Education UG - B.Tech/B.E. - Electronics/Telecomunication
PG - M.Tech - Electronics/Telecomunication
Compensation: As per Industry Standards
Location Delhi/NCR
Keywords like Simulation Platform, SOC Verification,Silicon level,CHD SOC , CHD Driver
Contact ST- HR
STMicroelectronics Pvt Ltd
Plot No. - 01, Knowledge Park -3,
Greater Noida
NOIDA,Uttar Pradesh,India 201308
Telephone 91-120-2352999
Website http://www.st.com/internet/com/home/home.jsp