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Great requirement SIM Engnr at QUALCOMM
Posted June 3, 2011
· 2 - 5 Years
Organization
QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.
QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.
Role
Designation:SIM Engineer
Job Description
The successful candidate will be contributing/ leading to the gate level verification effort of a complex chip, core and/or blocks and will be responsible for gate level simulation bring up, netlist compilation, timing and non-timing simulation verification.
Responsible for test pattern generation based on timing simulation and Post silicon debug. Also support silicon characterization.
The role will involve working with the design, verification and post silicon test team and will be responsible for test case/test scenario development for critical path based Fmax test cases.
Desired Profile
Minimum 2- 3 years experience in ASIC/System verification/gate level verification/post silicon testing
Expertise in verifying complex designs from system as well as block level, through design flow
Experience in VERA, MODELSIM, Debussy
Knowledge on Perl or any other scripting language
Understanding of RTL design/verification concept
Exposure to post silicon debug ATE testing / Bench/application testing
Experience with gate level simulation (timing/non-timing), Silicon debug (ATE/bench), knowledge on embedded RISC/ARM/DSP processor architecture is basic need. RTL design, Chip/block level verification using vera/system verilog is an added advantage. Candidate must have good initiative, project management skills with excellent written and oral communications skills.
Experience: 2 - 5 Years
Industry Type: Semiconductors/ Electronics
Role: Hardware Design Engnr
Functional Area :IT-Support, Telecom, Hardware
Education: UG - B.Tech/B.E. - Electrical, Electronics/Telecomunication
PG - M.Tech - Electrical, Electronics/Telecomunication
Location: Bengaluru/Bangalore
Keywords: post silicon debug, silicon characterization, post silicon testing, gate level verification, ate testing
Contact: Qualcomm
Website: http://www.qualcomm.co.in
Job Description
The successful candidate will be contributing/ leading to the gate level verification effort of a complex chip, core and/or blocks and will be responsible for gate level simulation bring up, netlist compilation, timing and non-timing simulation verification.
Responsible for test pattern generation based on timing simulation and Post silicon debug. Also support silicon characterization.
The role will involve working with the design, verification and post silicon test team and will be responsible for test case/test scenario development for critical path based Fmax test cases.
Desired Profile
Minimum 2- 3 years experience in ASIC/System verification/gate level verification/post silicon testing
Expertise in verifying complex designs from system as well as block level, through design flow
Experience in VERA, MODELSIM, Debussy
Knowledge on Perl or any other scripting language
Understanding of RTL design/verification concept
Exposure to post silicon debug ATE testing / Bench/application testing
Experience with gate level simulation (timing/non-timing), Silicon debug (ATE/bench), knowledge on embedded RISC/ARM/DSP processor architecture is basic need. RTL design, Chip/block level verification using vera/system verilog is an added advantage. Candidate must have good initiative, project management skills with excellent written and oral communications skills.
Experience: 2 - 5 Years
Industry Type: Semiconductors/ Electronics
Role: Hardware Design Engnr
Functional Area :IT-Support, Telecom, Hardware
Education: UG - B.Tech/B.E. - Electrical, Electronics/Telecomunication
PG - M.Tech - Electrical, Electronics/Telecomunication
Location: Bengaluru/Bangalore
Keywords: post silicon debug, silicon characterization, post silicon testing, gate level verification, ate testing
Contact: Qualcomm
Website: http://www.qualcomm.co.in