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Openings for Technical Lead At Intel
Organization
Intel Technology
Role
Experience:6 - 11 Years
Location:Bengaluru/Bangalore
Education:UG - B.Tech/B.E. - Electronics/Telecomunication PG - M.Tech - Electronics/Telecomunication
Industry Type:Semiconductors/ Electronics
Role:Tech Lead -Hardware Design
Functional Area:IT-Support, Telecom, Hardware
Desired Candidate Profile
Expertise in area of fullchip floorplanning, tape-in and experience with layout processes in 32nm and 22 nm is preferable.
Experience in SOC type designs is good to have.
Overall experience should include RTL to GDS flow at block level and deep understanding of full chip physical design flows
and methodologies and experience with leading industry standard tools preferably in ASIC design methodologies.
Good communication skills
Job Description
Technical Lead –
In this position, you will be responsible for leading the Fullchip layout or block level Register Transfer Level(RTL) to GDS
activities of Physical design team of Intel UMG India SOC designs. You will be working as an individual contributor as well
as participate in planning, and directing activities in engineering function to meet schedules, standards, and cost. You will
be cultivating and reinforcing appropriate group values, norms and behaviors. You will also be identifying and analyzing
problems, plans, tasks, and solutions, and providing guidance to team on tasks & resolving problems and be interface to
partner SOC teams. In addition you may be required to work as project lead in some activities.
You should possess a Bachelor of Science or B. Tech. degree in Electrical Engineering or a Master of Science or M. Tech
degree in Electrical Engineering with more than ten years of experience. Additional qualifications include:
Expertise in area of fullchip floorplanning, tape-in and experience with layout processes in 32nm and 22 nm is preferable.
Experience in SOC type designs is good to have.
Overall experience should include RTL to GDS flow at block level and deep understanding of full chip physical design flows
and methodologies and experience with leading industry standard tools preferably in ASIC design methodologies.
Good communication skills
Keywords: Fulchip Floorplan Integration
Contact Details
Company Name:Intel Technology India Pvt Ltd
Website:http://www.intel.com
Executive Name:HR
Email Address:[email protected]
Location:Bengaluru/Bangalore
Education:UG - B.Tech/B.E. - Electronics/Telecomunication PG - M.Tech - Electronics/Telecomunication
Industry Type:Semiconductors/ Electronics
Role:Tech Lead -Hardware Design
Functional Area:IT-Support, Telecom, Hardware
Desired Candidate Profile
Expertise in area of fullchip floorplanning, tape-in and experience with layout processes in 32nm and 22 nm is preferable.
Experience in SOC type designs is good to have.
Overall experience should include RTL to GDS flow at block level and deep understanding of full chip physical design flows
and methodologies and experience with leading industry standard tools preferably in ASIC design methodologies.
Good communication skills
Job Description
Technical Lead –
In this position, you will be responsible for leading the Fullchip layout or block level Register Transfer Level(RTL) to GDS
activities of Physical design team of Intel UMG India SOC designs. You will be working as an individual contributor as well
as participate in planning, and directing activities in engineering function to meet schedules, standards, and cost. You will
be cultivating and reinforcing appropriate group values, norms and behaviors. You will also be identifying and analyzing
problems, plans, tasks, and solutions, and providing guidance to team on tasks & resolving problems and be interface to
partner SOC teams. In addition you may be required to work as project lead in some activities.
You should possess a Bachelor of Science or B. Tech. degree in Electrical Engineering or a Master of Science or M. Tech
degree in Electrical Engineering with more than ten years of experience. Additional qualifications include:
Expertise in area of fullchip floorplanning, tape-in and experience with layout processes in 32nm and 22 nm is preferable.
Experience in SOC type designs is good to have.
Overall experience should include RTL to GDS flow at block level and deep understanding of full chip physical design flows
and methodologies and experience with leading industry standard tools preferably in ASIC design methodologies.
Good communication skills
Keywords: Fulchip Floorplan Integration
Contact Details
Company Name:Intel Technology India Pvt Ltd
Website:http://www.intel.com
Executive Name:HR
Email Address:[email protected]