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Required for Design engineer At AMD
Organization
AMD India plays a significant role in the design of microprocessors, Fusion SoCs, graphics and media solutions. AMD located in Hyderabad With top-tier engineering talent, state of the art facilities, and world class management, AMD India has been delivering world-class, cost-effective System-On-Chips (SOCs), Hardware and Software platforms and high quality Intellectual Property.
AMD India strives to recruit and retain the best talent, make AMD a great place to work, and be an integral part of the AMD family by continuing to contribute significantly to AMD's success.
AMD India strives to recruit and retain the best talent, make AMD a great place to work, and be an integral part of the AMD family by continuing to contribute significantly to AMD's success.
Role
Experience:3 - 8 Years
Location:Hyderabad / Secunderabad
Education:UG - B.Tech/B.E. - Computers, Electrical PG - M.Tech - Computers, Electrical
Industry Type:Semiconductors/ Electronics
Role:Software Developer
Functional Area:Embedded/EDA /VLSI/ASIC/Chip Design
Desired Candidate Profile
REQUIREMENTS
At least 3+ years experience in complex ASIC Design. Direct experience in SOC or Graphics/Video is plus.
Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL
design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
Have hands-on experience in Chiplevel Design/Integration activities.
Some Physical Design exposure required.
Should be able to Lead a team, and provide Technical mentoring and guidance to junior engineers.
Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification,
etc.
Some exposure to DFT is a strong plus.
Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD
placement, etc.
Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath
compilers is required.
Should have proficiency in flow development and scripting.
Expertise in Perl and Tcl is a must.
Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
Must have good communication & Analytical thinking skills.
Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.
Bachelor/Master/ Degree in Electrical or Computer Engineering
Job Description
REQUIREMENTS
At least 4+ years experience in complex ASIC Design. Direct experience in SOC or Graphics/Video is plus.
Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL
design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
Have hands-on experience in Chiplevel Design/Integration activities.
Some Physical Design exposure required.
Should be able to Lead a team, and provide Technical mentoring and guidance to junior engineers.
Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification,
etc.
Some exposure to DFT is a strong plus.
Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD
placement, etc.
Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath
compilers is required.
Should have proficiency in flow development and scripting.
Expertise in Perl and Tcl is a must.
Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
Must have good communication & Analytical thinking skills.
Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.
Bachelor/Master/ Degree in Electrical or Computer Engineering
Keywords: SOC, ASIC, synthesis, STA, timing clousure, RTL,formal, verification, physical design
Contact Details
Company Name:AMD Research and Development Center India Pvt Ltd
Executive Name:Ravi Guthula
Address:AMD Research and Development Center India Pvt Ltd
Plot No. 2/A , 8-2-269/10 , Trendset Towers ,
Road No. 2 , Banjara Hills
HYDERABAD,Andhra Pradesh,India 500034
Email Address:[email protected]
Telephone:91-40-30615000
Location:Hyderabad / Secunderabad
Education:UG - B.Tech/B.E. - Computers, Electrical PG - M.Tech - Computers, Electrical
Industry Type:Semiconductors/ Electronics
Role:Software Developer
Functional Area:Embedded/EDA /VLSI/ASIC/Chip Design
Desired Candidate Profile
REQUIREMENTS
At least 3+ years experience in complex ASIC Design. Direct experience in SOC or Graphics/Video is plus.
Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL
design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
Have hands-on experience in Chiplevel Design/Integration activities.
Some Physical Design exposure required.
Should be able to Lead a team, and provide Technical mentoring and guidance to junior engineers.
Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification,
etc.
Some exposure to DFT is a strong plus.
Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD
placement, etc.
Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath
compilers is required.
Should have proficiency in flow development and scripting.
Expertise in Perl and Tcl is a must.
Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
Must have good communication & Analytical thinking skills.
Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.
Bachelor/Master/ Degree in Electrical or Computer Engineering
Job Description
REQUIREMENTS
At least 4+ years experience in complex ASIC Design. Direct experience in SOC or Graphics/Video is plus.
Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL
design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
Have hands-on experience in Chiplevel Design/Integration activities.
Some Physical Design exposure required.
Should be able to Lead a team, and provide Technical mentoring and guidance to junior engineers.
Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification,
etc.
Some exposure to DFT is a strong plus.
Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD
placement, etc.
Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath
compilers is required.
Should have proficiency in flow development and scripting.
Expertise in Perl and Tcl is a must.
Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
Must have good communication & Analytical thinking skills.
Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.
Bachelor/Master/ Degree in Electrical or Computer Engineering
Keywords: SOC, ASIC, synthesis, STA, timing clousure, RTL,formal, verification, physical design
Contact Details
Company Name:AMD Research and Development Center India Pvt Ltd
Executive Name:Ravi Guthula
Address:AMD Research and Development Center India Pvt Ltd
Plot No. 2/A , 8-2-269/10 , Trendset Towers ,
Road No. 2 , Banjara Hills
HYDERABAD,Andhra Pradesh,India 500034
Email Address:[email protected]
Telephone:91-40-30615000
Contact
Ravi Guthula