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Sr Physical Design Engnr Required @ Applied Micro
Organization
Applied Micro (APM) is a global leader in network and embedded Power Architecture processing, optical transport and storage solutions. Our products enable the development of converged IP-based networks offering high-speed secure data, high-definition video and high-quality voice for carrier, metropolitan, access and enterprise applications. APM provides networking equipment vendors with industry-leading network and communications processing, Ethernet, SONET, OTN and switch fabric solutions. APM's 3ware SAS and SATA RAID product families deliver cost-effective, high-performance, high-capacity storage for enterprises and consumers worldwide for applications from the desktop to the data center. APM's corporate headquarters are located in Sunnyvale, California. Sales and engineering offices are located throughout the world.
About APM India:
APM has commenced its India Design Center in Dec 2008 with a view to tap the ample talent in the VLSI domain and for embedded software development and QA. Based in Kalyaninagar, Pune, the state of the art facility would house multiple teams for SOC RTL design and verification, high speed board design, validation, embedded software development and QA of the same. In near future, it would be the largest development center outside of USA.
The high caliber team is expected to work on the various products of APM based on very top end architectures using PowerPC cores. Its leadership in 10 Gigabit Ethernet and other Storage technologies makes it a very exciting place to be.
About APM India:
APM has commenced its India Design Center in Dec 2008 with a view to tap the ample talent in the VLSI domain and for embedded software development and QA. Based in Kalyaninagar, Pune, the state of the art facility would house multiple teams for SOC RTL design and verification, high speed board design, validation, embedded software development and QA of the same. In near future, it would be the largest development center outside of USA.
The high caliber team is expected to work on the various products of APM based on very top end architectures using PowerPC cores. Its leadership in 10 Gigabit Ethernet and other Storage technologies makes it a very exciting place to be.
Role
Experience:2 - 7 Years
Location:Pune
Education:UG - B.Tech/B.E. - Computers, Electrical, Electronics/Telecomunication PG - M.Tech - Computers, Electrical, Electronics/Telecomunication
Industry Type:Semiconductors/ Electronics
Role:Team Lead/Tech Lead
Functional Area:Embedded/EDA /VLSI/ASIC/Chip Design
Desired Candidate Profile
Position: Senior Physical Design Engineer
Location: Pune
This position is targeted towards the role of block owner in the area of physical design for implementing physical design using Gate level netlist to GDS ASIC design flows for cutting edge technologies.
• The physical design engineer will be responsible for the execution of all SoC or Transport physical design activities for APM's next generation products
• She/he will be responsible for execution of Physical Design (place and route) duties at block level, IP/macro level, as well as supporting chip-level activities.
• This includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Logical vs. Schematic (LVS) checks.
• Expertise in Place and Route flow i.e. Floorplanning, powerplanning, placement, CTS,routing and closing timing at each stage including crosstalk.
• Expertise in physical verification i.e. DRC/LVS using Mentor caliber.
• Understanding and implementation knowledge of Low power,OCV, DFM, DFY,EM and IR Drop.
• Understanding of Deep Submicron effects such as 90nm and below.
• Hands on recent or past experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools.
• Self-motivated, conflict resolution skills, and experience working with global teams across time zones.
• Understanding of programming language such as TCL,Perl,AWK,Shell and have used their implementation in flow automation.
Job Description
Applied Micro is a global leader in Energy Conscious Computing & Communications solutions for Datacenter,Telecom,Enterprise Applications. This position is targeted towards the role of block owner in the area of physical design for implementing physical design using Gate level netlist to GDS ASIC design flows for cutting edge technologies.
Keywords: Physical Design, Backend Design, Cadence, Synopsys, Magma, Mentor Graphics, DRC, LVS, floor planning, placement, scan - reordering, clock tree, synthesis, timing analysis, timing closure, Place and route, PnR, P&R, BlastFusion, Blastplan, Talus, D
Contact
Kapil
The Human Capital
http://www.thehumancapital.net
[email protected]
9810199914
Contact Details
Company Name:Applied Micro
Website:http://www.thehumancapital.net
Executive Name:Kapil
Email Address:[email protected]
Location:Pune
Education:UG - B.Tech/B.E. - Computers, Electrical, Electronics/Telecomunication PG - M.Tech - Computers, Electrical, Electronics/Telecomunication
Industry Type:Semiconductors/ Electronics
Role:Team Lead/Tech Lead
Functional Area:Embedded/EDA /VLSI/ASIC/Chip Design
Desired Candidate Profile
Position: Senior Physical Design Engineer
Location: Pune
This position is targeted towards the role of block owner in the area of physical design for implementing physical design using Gate level netlist to GDS ASIC design flows for cutting edge technologies.
• The physical design engineer will be responsible for the execution of all SoC or Transport physical design activities for APM's next generation products
• She/he will be responsible for execution of Physical Design (place and route) duties at block level, IP/macro level, as well as supporting chip-level activities.
• This includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Logical vs. Schematic (LVS) checks.
• Expertise in Place and Route flow i.e. Floorplanning, powerplanning, placement, CTS,routing and closing timing at each stage including crosstalk.
• Expertise in physical verification i.e. DRC/LVS using Mentor caliber.
• Understanding and implementation knowledge of Low power,OCV, DFM, DFY,EM and IR Drop.
• Understanding of Deep Submicron effects such as 90nm and below.
• Hands on recent or past experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools.
• Self-motivated, conflict resolution skills, and experience working with global teams across time zones.
• Understanding of programming language such as TCL,Perl,AWK,Shell and have used their implementation in flow automation.
Job Description
Applied Micro is a global leader in Energy Conscious Computing & Communications solutions for Datacenter,Telecom,Enterprise Applications. This position is targeted towards the role of block owner in the area of physical design for implementing physical design using Gate level netlist to GDS ASIC design flows for cutting edge technologies.
Keywords: Physical Design, Backend Design, Cadence, Synopsys, Magma, Mentor Graphics, DRC, LVS, floor planning, placement, scan - reordering, clock tree, synthesis, timing analysis, timing closure, Place and route, PnR, P&R, BlastFusion, Blastplan, Talus, D
Contact
Kapil
The Human Capital
http://www.thehumancapital.net
[email protected]
9810199914
Contact Details
Company Name:Applied Micro
Website:http://www.thehumancapital.net
Executive Name:Kapil
Email Address:[email protected]
Contact
Kapil