| Boundary Scan Description Language, BSDL |
Boundary Scan Description Language, BSDL
an overview of the boundary scan description language, used in the
development of boundary scan tests.
Boundary scan is now a well established test technology.
Boundary scan has been in use since the early 1990s when the Joint Test Action
Group (JTAG) devised a solution to testing the many new boards that were being
developed and manufactured where there was little access for test. With boundary
scan established, a further step was to develop a standard language that could
be used in the creation of boundary scan tests. With this, the boundary scan
development language was created.
A D V E R T I S E M E N T
The Boundary Scan Description Language, BSDL, has been
designed as the standard programming language for boundary scan devices that
comply with IEEE 1149.1-1990, and the intention that it should be used by
boundary scan test developers, device manufacturers, ASIC designers, ATE
manufacturers and anyone using boundary scan. The aim is that BSDL will promote
consistency throughout the electronics industry. Additionally, it will enable
the specification of any boundary scan functions on a device in a more useful
and consistent manner.
Introduction of BSDL
The Boundary Scan Description Language came out of the
development of the boundary scan test philosophy. The initial IEE 1149.1
standard describing boundary scan was approved and released in 1990, and as a
result the use of boundary scan techniques started to grow. The next revision of
the standard occurred in 1993, but in 1994 another revision occurred, and this
incorporated the Boundary Scan Description Language.
What is BSDL?
The Boundary Scan Description Language enables users to
provide a description of the way in which boundary scan applies to different
devices. As each user will tend to apply the boundary scan standard in a
slightly different way, it is necessary to express tests in a comprehensible,
specific and usable fashion.
BSDL is written within a subset of VHDL. VHDL or VHSIC
Hardware Description Language, is commonly used as a
design-entry language for FPGAs and ASICs in electronic design automation of
digital circuits, and as such it is ideal for work with boundary scan because
design of many chips is performed using this language. However BSDL is a "subset
and standard practice" of VHDL, i.e. the scope of VHDL is limited for this
application.
During the design of BSDL there were two main criteria for
the language:
- it should be easy to use
- it should be parsable by a computer in a simple and unambiguous fashion
BDSL enables accurate and useful descriptions of the features
of a device that uses boundary scan. The language can be used by the boundary
scan tools to make use of the device features to enable test programme
generation, failure diagnosis as well as being used in any testability analysis.
Although the Boundary Scan Description Language, BSDL, is not
a language that can be sued for hardware descriptions, but a language that can
be used to define the data transport characteristics of the device, i.e. how it
captures, shifts, and updates data. This is then used in defining the test
capability.
The BSDL file includes the following data:
- Entity Declaration: The Entity Declaration is a VHDL
construction that is used to identify the name of the device that is
described by the BSDL file.
- Generic Parameter: The Generic Parameter is the section of the
BSDL file that specifies which package is described.
- Logical Port Description: This description lists all the
connections on the device. It defines its basic attributes, i.e. whether the
connection is an input (in bit;), output (out bit;), bi-directional (in-out
bit;) or if it is unavailable for boundary scan (linkage bit;).
- Package Pin Mapping: The Package Pin Mapping is used for
determining the internal connections within an integrated circuit. It
details how the pads on the device die are wired to the external pins.
- Use statements: This statement is used to call the VHDL
packages that contain the data that are referenced in the BSDL File.
- Scan Port Identification: The Scan Port Identification
identifies the particular pins that are used for the boundary scan / JTAG
implementation. These include: TDI, TDO, TMS, TCK and TRST (if used).
- TAP description: This entity provides additional information on
the boundary scan or JTAG logic for the device. The data included comprises:
the Instruction Register length, Instruction Opcodes, device IDCODE, etc.
- Boundary Register description: This description provides the
structure of the Boundary Scan cells on the device. Each pin on a device may
have up to three Boundary Scan cells, each cell consisting of a register and
a latch.
Summary
The Boundary Scan Description Language, BSDL, is widely used
within the JTAG, boundary scan community to enable consistent, accurate and
useful information to be defined for a boundary scan enabled device. In this
way, the chip can be incorporated into a design, and its capabilities used to
their full in the most efficient manner.
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